TSMC N3 series process is unable to increase SRAM density and is no longer related to the increase in logical density

Last month, TSMC introduced a roadmap for advanced semiconductor manufacturing processes, including various processes at 3nm and 2nm process nodes. This year, TSMC will launch an improved N3E process with lower costs and better economic benefits. Next, it will provide a wider product portfolio at 3nm process nodes, including N3P, N3X, and N3AE, to meet the diverse needs of different customers.

WikiChip stated that recent information shows that SRAM units are located on TSMC's 3nm process node and have little difference from the 5nm process node. Although TSMC had previously stated that the density of SRAM cells in the new process nodes is 1.2 times higher than the previous generation process, according to the latest information, the difference is very small. Previously, there were reports that TSMC encountered a slowdown in SRAM unit reduction at 3nm process nodes.

It is understood that TSMC has introduced the SAC scheme adopted by Intel as early as 2011 at 22nm in its improved N3E process, which has improved the yield rate. However, no matter how the N3E process is improved, the density of SRAM units does not differ significantly. This has also led TSMC to intentionally avoid the issue of improving logical density and manufacturing steps when discussing the progress of new process nodes today.

In modern processors, SRAM occupies a large portion of the chip area and the number of transistors. If there is no significant improvement, the effect of replacing the chip with a new process node is not very obvious. Moreover, TSMC's 3nm process node costs have skyrocketed, leading many chip companies to choose to wait and see and not place orders. In fact, SRAM reduction has no longer followed the increase in logical density for a period of time, but the two are no longer closely related.